Field of the Invention
The present invention relates to vertical field effect transistors (VFETs) and, more particularly, a VFET with a combined gate/gate extension structure that is self-aligned and a method of forming the VFET.
Description of Related Art
Integrated circuit (IC) design decisions are often driven by device scalability, device density, manufacturing efficiency and costs. For example, size scaling of planar field effect transistors (FETs) resulted in the development of planar FETs with relatively short channel lengths. Unfortunately, the smaller channel lengths resulted in a corresponding increase in short channel effects. In response, non-planar FET technologies have been developed.
Exemplary non-planar technologies include, for example, standard fin-type FETs (FINFETs) and vertical fin-type FETs (VFETs). A FINFET is a non-planar FET that incorporates a semiconductor fin (i.e., a relatively tall and thin, initial, rectangular-shaped, semiconductor body) and, within the semiconductor fin, a channel region positioned laterally between source/drain regions. A gate is positioned adjacent to the top surface and opposing sidewalls of the semiconductor fin at the channel region. A VFET is a non-planar FET that also incorporates a semiconductor fin (i.e., a relatively tall and thin, rectangular-shaped, semiconductor body). In this case, the FET components are stacked vertically on a substrate as opposed to being positioned side by side across a substrate in order to allow for increased device density (i.e., a greater number of devices within a given area). Specifically, a VFET typically includes a lower source/drain region in a substrate, a semiconductor fin that extends upward from the lower source/drain region, and an upper source/drain region that is epitaxially grown on the top surface of the semiconductor fin. A gate (e.g., a metal gate) laterally surrounds the semiconductor fin, which functions as the channel region, and is electrically isolated from the lower source/drain region and the upper source/drain region by lower and upper spacer layers, respectively. Each of these non-planar FET technologies consumes less chip surface area than a planar FET. Additionally, they exhibit multi-dimensional field effects as compared to the single-dimensional field effects exhibited by a planar FET and, thus, exhibit improved gate control over the channel.
As the device density (i.e., the number of devices per unit area) of IC designs continues to be increased, forming the above-mentioned non-planar FETs without violating design rules and/or risking the formation of defects (e.g., shorts) can be difficult. For example, recently IC designs have been developed with a reduced fin pitch of 36 nm or less in order to increase device density in an array of VFETs. This reduction in fin pitch necessarily requires a corresponding reduction in the gate pitch to minimize parasitic capacitance. One recently developed technique for reducing gate pitch is the formation of a self-aligned gate. However, the resulting self-aligned gate will be aligned below the upper source/drain region and, thus, a gate extension must also be formed immediately adjacent to the gate in order to provide a landing surface for the gate contact. Unfortunately, the added extension consumes additional chip area and, thus, cancels out any scaling benefit that could be achieved by reducing the fin pitch and the gate pitch.